Session Chair: Benny Åkesson
Thursday, July 9, 14:30 – 15:10 (CET) and 15:50 – 16:50 (CET)
Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs
Francesco Restuccia, Marco Pagani, Alessandro Biondi, Mauro Marinoni, and Giorgio Buttazzo
On How to Identify Cache Coherence: Case of the NXP QorIQ T4240
Nathanaël Sensfelder, Julien Brunel, and Claire Pagetti
Simultaneous Multithreading and Hard Real Time: Can it be Safe?
Sims Hill Osborne and James H. Anderson
Tracing Hardware Monitors in the GR712RC Multicore Platform: Challenges and Lessons Learnt from a Space Case Study
Xavier Palomo, Mikel Fernandez, Sylvain Girbal, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla, and Laurent Rioux
Discriminative Coherence: Balancing Performance and Latency Bounds in Data-sharing Multi-Core Real-Time Systems
Mohamed Hassan