On How to Identify Cache Coherence: Case of the NXP QorIQ T4240

Nathanaël Sensfelder, Julien Brunel, Claire Pagetti

Architectures used in safety critical systems have to pass certain certification standards, which require sufficient proof that they will behave as expected. Multi-core processors make this challenging by featuring complex interactions between the tasks they run. A lot of these interactions are made without explicit instructions from the program designers. Furthermore, they can have strong negative impacts on performance (and potentially affect correctness). One important such source of interactions is cache coherence, which speeds up operations in most cases, but can also lead to unexpected variations in execution time if not fully understood. Architecture documentations often lack details on the implementation of cache coherence. We thus propose a strategy to ascertain that the platform does indeed implement the cache coherence protocol its user believes it to. We also apply this strategy to the NXP QorIQ T4240, resulting in the identification of a protocol (MESIF) other than the one this architecture’s documentation led us to believe it was using (MESI).

The paper will be presented in the session
Hardware I Busses in FPGAs and Cache coherence – Thursday, July 9, 14:30 – 15:10 (CET) and 15:50 – 16:50 (CET)


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