Jan Reineke

Real-Time and Embedded Systems Lab
Saarland University
Saarland Informatics Campus
Phone: +49 681 302 4448
eMail:
Building: E 1 3 Room: 410
Coordinates: N 49.257833° E 7.045144°

Administrative Assistant: Sandra Neumann
Phone: +49 681 302 3434
Building: E 1 3 Room: 430

Office Hour: Wednesday 16:00-17:00

I am looking for PhD students and postdocs!
If you are interested, please feel free to get in touch. The topic is relatively flexible as long as it is aligned with my research interests...

I am always looking for student assistants.
If you are interested in working with me and my group or if you are looking for a Bachelor or Master thesis topic, please feel free to stop by my office or to drop me an email.

Short CV

Jan Reineke is a professor of computer science at Saarland University. Before joining Saarland University in 2012, he has been a postdoctoral scholar at UC Berkeley in the Ptolemy group from 2009 to 2011. He completed his MSc and PhD in Computer Science at Saarland University in 2005 and 2008, respectively, and his BSc in Computing Science at the University of Oldenburg in 2003.

His research centers around problems at the boundary between hardware and software.

In the area of real-time systems, he is particularly interested in principles for the design of timing-predictable hardware and in precise and efficient timing-analysis techniques for multi-core architectures. His recent results include the design of the first provably timing-predictable pipelined processor design (RTSS 2018) and the first exact analyses for LRU caches (CAV 2017, POPL 2019).

Another focus of his work are security vulnerabilities of hardware-software systems. Recent results include the development of automatic techniques to detect information leaks introduced by speculative execution (Spectector), techniques to quantify the information leakage through cache side channels (ACM TISSEC 2015), and automatic methods to obtain highly detailed performance models for modern microarchitectures (ASPLOS 2019).

In 2012, he was selected as an Intel Early Career Faculty Honor Program awardee. He was the PC chair of EMSOFT 2014, the International Conference on Embedded Software, a Topic co-chair at DATE 2016 and the PC chair of WCET 2017, the International Workshop on Worst-Case Execution Time Analysis. His papers have been awarded 5 outstanding paper awards and one best-paper nomination at conferences including RTSS and ECRTS.

Selected Recent Publications

Spectector: Principled Detection of Speculative Information Flows
M. Guarnieri, B. Köpf, J. Morales, J. Reineke, and A. Sanchez
IEEE Symposium on Security & Privacy, 2020. [pdf] [web] [bib]

@INPROCEEDINGS{Guarnieri20,
  author    = {Marco Guarnieri and
               Boris K{\"{o}}pf and
               Jos{\'{e}} F. Morales and
               Jan Reineke and
               Andr{\'{e}}s S{\'{a}}nchez},
  title     = {{SPECTECTOR:} Principled Detection of Speculative Information Flows},
  booktitle = {2020 {IEEE} Symposium on Security and Privacy, {SP} 2020, Proceedings, San Francisco, California, {USA}},  
  year      = {2020},
  month	    = {May},
  url       = {https://spectector.github.io/papers/spectector.pdf},
}

uops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on Intel Microarchitectures
A. Abel and J. Reineke
ASPLOS, 2019. [pdf] [bib]

@INPROCEEDINGS{Abel19,
    author = {Andreas Abel and Jan Reineke},
    title = {uops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on Intel Microarchitectures},
    booktitle = {ASPLOS},
    year = {2019},
    month = {April},
    url = {https://arxiv.org/pdf/1810.04610.pdf},
}

Fast and Exact Analysis for LRU Caches
V. Touzeau, C. Maiza, D. Monniaux, and J. Reineke
POPL, 2019. [url] [doi] [bib]

@article{Touzeau19,
 author = {Touzeau, Valentin and Ma\"{\i}za, Claire and Monniaux, David and Reineke, Jan},
 title = {Fast and Exact Analysis for LRU Caches},
 journal = {Proc. ACM Program. Lang.},
 issue_date = {January 2019},
 volume = {3},
 number = {POPL},
 month = jan,
 year = {2019},
 issn = {2475-1421},
 pages = {54:1--54:29},
 articleno = {54},
 numpages = {29},
 url = {http://doi.acm.org/10.1145/3290367},
 doi = {10.1145/3290367},
 acmid = {3290367},
 publisher = {ACM},
 address = {New York, NY, USA},
 keywords = {Abstract Interpretation, Cache Analysis, LRU},
}

Basic Problems in Multi-View Modeling
J. Reineke, C. Stergiou, and S. Tripakis
Software & Systems Modeling, 18(3) 2019. [doi] [bib]

@article{Reineke19,
  author    = {Jan Reineke and
               Christos Stergiou and
               Stavros Tripakis},
  title     = {Basic problems in multi-view modeling},
  journal   = {Software and System Modeling},
  volume    = {18},
  number    = {3},
  pages     = {1577--1611},
  year      = {2019},
  url       = {https://doi.org/10.1007/s10270-017-0638-1},
  doi       = {10.1007/s10270-017-0638-1},
}

Design and Analysis of SIC: A Provably Timing-Predictable Pipelined Processor Core (Best Student Paper Award )
S. Hahn and J. Reineke
RTSS, 2018. [pdf] [pdf slides] [bib]

@INPROCEEDINGS{Hahn18,
    author = {Sebastian Hahn and Jan Reineke},
    title = {Design and Analysis of SIC: A Provably Timing-Predictable Pipelined Processor Core},
    booktitle = {RTSS},
    year = {2018},
    month = {December},
}

The Semantic Foundations and a Landscape of Cache-Persistence Analyses
J. Reineke
Leibniz Transactions on Embedded Systems, 2018. [doi] [bib]

@article{Reineke18a,
  author    = {Jan Reineke},
  title     = {The Semantic Foundations and a Landscape of Cache-Persistence Analyses},
  journal   = {{LITES}},
  volume    = {5},
  number    = {1},
  pages     = {03:1--03:52},
  year      = {2018},
  url       = {https://doi.org/10.4230/LITES-v005-i001-a003},
  doi       = {10.4230/LITES-v005-i001-a003},
}

An Extensible Framework for Multicore Response Time Analysis
R. Davis, S. Altmeyer, L. Indrusiak, C. Maiza, V. Nelis, and J. Reineke
Real-Time Systems, July 2018. [doi] [bib]

@Article{Davis18a,
	author="Davis, Robert I.
		and Altmeyer, Sebastian
		and Indrusiak, Leandro S.
		and Maiza, Claire
		and Nelis, Vincent
		and Reineke, Jan",
	title="An extensible framework for multicore response time analysis",
	journal="Real-Time Systems",
	year="2018",
	month="Jul",
	day="01",
	volume="54",
	number="3",
	pages="607--661",
	issn="1573-1383",
	doi="10.1007/s11241-017-9285-4",
	url="https://doi.org/10.1007/s11241-017-9285-4"
}

On the Smoothness of Paging Algorithms
J. Reineke and A. Salinger
Theory of Computing Systems, February 2018. [doi] [bib]

@Article{Reineke18,
author="Reineke, Jan
and Salinger, Alejandro",
title="On the Smoothness of Paging Algorithms",
journal="Theory of Computing Systems",
year="2018",
month="Feb",
day="01",
volume="62",
number="2",
pages="366--418",
abstract="We study the smoothness of paging algorithms. How much can the number of page faults increase due to a perturbation of the request sequence? We call a paging algorithm smooth if the maximal increase in page faults is proportional to the number of changes in the request sequence. We also introduce quantitative smoothness notions that measure the smoothness of an algorithm. We derive lower and upper bounds on the smoothness of deterministic and randomized demand-paging and competitive algorithms. Among strongly-competitive deterministic algorithms, LRU matches the lower bound, while FIFO matches the upper bound. Well-known randomized algorithms such as Partition, Equitable, or Mark are shown not to be smooth. We introduce two new randomized algorithms, called Smoothed-LRU and LRU-Random. Smoothed-LRU allows sacrificing competitiveness for smoothness, where the trade-off is controlled by a parameter. LRU-Random is at least as competitive as any deterministic algorithm but smoother.",
issn="1433-0490",
doi="10.1007/s00224-017-9813-6",
url="https://doi.org/10.1007/s00224-017-9813-6"
}

Abstract PRET Machines
E. A. Lee, J. Reineke, and M. Zimmer
RTSS, 2017. [doi] [bib]

@inproceedings{Lee17,
  author    = {Edward A. Lee and
               Jan Reineke and
               Michael Zimmer},
  title     = {Abstract {PRET} Machines},
  booktitle = {2017 {IEEE} Real-Time Systems Symposium, {RTSS} 2017, Paris, France,
               December 5-8, 2017},
  pages     = {1--11},
  year      = {2017},
  url       = {http://doi.ieeecomputersociety.org/10.1109/RTSS.2017.00041},
  doi       = {10.1109/RTSS.2017.00041},
}

Ascertaining Uncertainty for Efficient Exact Cache Analysis
V. Touzeau, C. Maiza, D. Monniaux, and J. Reineke
CAV, 2017. [pdf] [bib]

@INPROCEEDINGS{Touzeau17,
    author = {Valentin Touzeau and Claire Maiza and David Monniaux and Jan Reineke},
    title = {Ascertaining Uncertainty for Efficient Exact Cache Analysis},
    booktitle = {CAV},
    year = {2017},
    month = {July},
    url = {http://embedded.cs.uni-saarland.de/publications/AscertainingUncertaintyForEfficientExactCacheAnalysisCAV2017.pdf},
}

Write-back Caches in WCET Analysis (Outstanding Paper Award )
T. Blaß, S. Hahn, and J. Reineke
ECRTS, 2017. [doi] [pdf] [pdf slides] [bib]

@inproceedings{Blass17,
  author    = {Tobias Bla{\ss} and
               Sebastian Hahn and
               Jan Reineke},
  title     = {Write-Back Caches in {WCET} Analysis},
  booktitle = {29th Euromicro Conference on Real-Time Systems, {ECRTS} 2017, June
               27-30, 2017, Dubrovnik, Croatia},
  pages     = {26:1--26:22},
  year      = {2017},
  url       = {https://doi.org/10.4230/LIPIcs.ECRTS.2017.26},
  doi       = {10.4230/LIPIcs.ECRTS.2017.26},
}

Enabling Compositionality for Multicore Timing Analysis
S. Hahn, M. Jacobs, and J. Reineke
RTNS, 2016. [doi] [pdf] [bib]

@INPROCEEDINGS{Hahn16,
    author = {Sebastian Hahn and Michael Jacobs and Jan Reineke},
    title = {Enabling Compositionality for Multicore Timing Analysis},
    booktitle = {Proceedings of the 24th International Conference on Real Time and Networks Systems},
    year = {2016},
    month = {October},
    url = {http://embedded.cs.uni-saarland.de/publications/EnablingCompositionalityRTNS2016.pdf},
    doi = {10.1145/2997465.2997471},
}

Gray-box Learning of Serial Compositions of Mealy Machines
A. Abel and J. Reineke
NFM, 2016. [doi] [pdf] [bib]

@INPROCEEDINGS{Abel16,
    author = {Andreas Abel and Jan Reineke},
    title = {Gray-box Learning of Serial Compositions of Mealy Machines},
    booktitle = {Nasa Formal Methods Symposium},
    year = {2016},
    month = {June},
    doi = {10.1007/978-3-319-40648-0_21},
}

MeMin: SAT-based Exact Minimization of Incompletely Specified Mealy Machines
A. Abel and J. Reineke
ICCAD, 2015. [doi] [pdf] [bib]

@inproceedings{Abel15,
  author    = {Andreas Abel and
               Jan Reineke},
  title     = {MeMin: SAT-based Exact Minimization of Incompletely Specified Mealy
               Machines},
  booktitle = {Proceedings of the {IEEE/ACM} International Conference on Computer-Aided
               Design, {ICCAD} 2015, Austin, TX, USA, November 2-6, 2015},
  pages     = {94--101},
  year      = {2015},
  url       = {http://dx.doi.org/10.1109/ICCAD.2015.7372555},
  doi       = {10.1109/ICCAD.2015.7372555},
}

CacheAudit: A Tool for the Static Analysis of Cache Side Channels
G. Doychev, B. Köpf, L. Mauborgne, and J. Reineke
ACM Transactions on Information and System Security, 18(1), June 2015. [doi] [pdf] [bib]

@article{Doychev15,
 author = {Doychev, Goran and K\"{o}pf, Boris and Mauborgne, Laurent and Reineke, Jan},
 title = {CacheAudit: A Tool for the Static Analysis of Cache Side Channels},
 journal = {ACM Trans. Inf. Syst. Secur.},
 issue_date = {June 2015},
 volume = {18},
 number = {1},
 month = jun,
 year = {2015},
 issn = {1094-9224},
 pages = {4:1--4:32},
 articleno = {4},
 numpages = {32},
 url = {http://doi.acm.org/10.1145/2756550},
 doi = {10.1145/2756550},
 acmid = {2756550},
 publisher = {ACM},
 address = {New York, NY, USA},
 keywords = {Side-channel attacks, caches},
}

Towards Compositionality in Execution Time Analysis - Definition and Challenges
S. Hahn, J. Reineke, and R. Wilhelm
SIGBED Review, 12 (1), 2015. [doi] [pdf] [bib]

@article{Hahn15,
  author    = {Sebastian Hahn and
               Jan Reineke and
               Reinhard Wilhelm},
  title     = {Towards compositionality in execution time analysis: definition and
               challenges},
  journal   = {{SIGBED} Review},
  volume    = {12},
  number    = {1},
  pages     = {28--36},
  year      = {2015},
  url       = {http://doi.acm.org/10.1145/2752801.2752805},
  doi       = {10.1145/2752801.2752805},
  timestamp = {Sat, 25 Apr 2015 19:50:05 +0200},
  biburl    = {http://dblp.uni-trier.de/rec/bib/journals/sigbed/0001RW15},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}

Publications

A list of all of my publications can be found here and on DBLP.

Recent and Upcoming Professional Activities

MEMOCODE 2019 (PC Member)
RTAS 2014 (Track 2), 2015 (Track 1), 2016 (Track 3), 2018 (Track 3), 2019 (Track 3) (PC Member)
WCET 2017 (PC Chair) 2018 (PC Member)
FORMATS 2017 (PC Member)
ECRTS 2017, 2018 (PC Member)
RTSS 2016, 2017 (PC Member)
RTNS 2016 (PC Member)
DATE 2016 (PC Topic Co-Chair)
DATE 2015, 2016 (PC Member)
EMSOFT 2015 (PC Member)
EMSOFT 2014 (PC Co-Chair)

Real-Time and Embedded Systems Lab