Sebastian HahnReal-Time and Embedded Systems Lab |
Short CV
I joined the group of Jan Reineke in 2013.
Prior to that, I worked on relational cache analysis in the group of Reinhard Wilhelm advised by Daniel Grund.
I completed my B.Sc. on relational cache analysis in late 2011.
Since 2012, I am a member of the Graduate School of Computer Science at Saarland University.
I received my M.Sc. on a formal definition of timing compositionality in early 2015.
Until the end of 2015, I was part of the DFG SFB/TR 14 Automatic Verification and Analysis of Complex Systems working on timing compositionality.
From 2017 on, I work on timing-predictable processor designs and corresponding timing analyses within the DFG project "PEP: Precise and Efficient Prediction of Good Worst-case Performance for Contemporary and Future Architectures".
Research Interests
- Embedded Systems
- Static Program Analysis, especially Timing Analysis
- Computer Architecture, especially in the context of timing predictability
- Timing compositionality
Teaching
Winter 2016/2017, Winter 2018/2019
- Seminar: Hardware Design
Summer 2015, Winter 2017/2018
- Advanced Course: Verification of Real-Time Systems
Summer 2014, Summer 2016, Summer 2017
- Basic Course: Systemarchitektur
Winter 2012/2013
- Advanced Course: Development of Safety-Critical Embedded Systems
Summer 2012
- Core Course: Embedded Systems
Thesis Advisor
- Claus Faymonville
Evaluating compositional timing analyses
Master Thesis, Saarland University, 2015 - Benjamin Meyer
Development of a Controller for the Automated Reconnection of Trolleybus Poles
Master Thesis, Saarland University, 2015 - Tobias Blaß
Array-aware Cache Analysis for Write-through and Write-back Caches
Master Thesis, Saarland University, 2016
Publications
- Design and Analysis of SIC: A Provably Timing-Predictable Pipelined Processor Core (Best Student Paper Award)
S. Hahn and J. Reineke
RTSS, 2018. [pdf slides] [bib]
- Experimental Evaluation of Cache-Related Preemption Delay Aware Timing Analysis
D. Shah, S. Hahn, and J. Reineke
WCET, 2018. [bib]
- Write-back Caches in WCET Analysis
T. Blaß, S. Hahn, and J. Reineke
ECRTS, 2017. [bib]
- Enabling Compositionality for Multicore Timing Analysis
S. Hahn, M. Jacobs, and J. Reineke
RTNS, 2016. [doi] [bib]
- WCET Analysis for Multi-core Processors with Shared Buses and Event-driven Bus Arbitration
M. Jacobs, S. Hahn, and S. Hack
RTNS, 2015. [doi] [pdf] [bib]
- Toward Compact Abstractions for Processor Pipelines
S. Hahn, J. Reineke, and R. Wilhelm
Correct System Design, 2015. [doi] [bib]
- Towards Compositionality in Execution Time Analysis - Definition and Challenges
S. Hahn, J. Reineke, and R. Wilhelm
SIGBED Review, Special Issue on CRTS 2013, 12 (1), 2015. [doi] [bib]
- Selfish-LRU: Preemption-Aware Caching for Predictability and Performance
J. Reineke, S. Altmeyer, D. Grund, S. Hahn, C. Maiza
RTAS, 2014. [pdf] [pdf slides] [bib]
- Towards Compositionality in Execution Time Analysis - Definition and Challenges
S. Hahn, J. Reineke, and R. Wilhelm
CRTS, 2013. [pdf] [bib]
- Impact of Resource Sharing on Performance and Performance Prediction: A Survey
A. Abel, F. Benz, J. Doerfert, B. Dörr, S. Hahn, F. Haupenthal, M. Jacobs, A. H. Moin, J. Reineke, B. Schommer, and R. Wilhelm
CONCUR, 2013. [pdf] [bib]
- Relational Cache Analysis for Static Timing Analysis
S. Hahn and D. Grund
ECRTS, 2012. [pdf] [slides] [bib]
A list of publications can also be found on DBLP.