Workshop Chairs
Jean-Luc Scharbarg
Université de Toulouse - IRIT/INPT/ENSEEIHT, France
Jean-Luc dot Scharbarg at enseeiht dot fr
Mathieu Jan
CEA LIST, France
Mathieu dot Jan at cea dot fr
Program Committee
Frédéric Ridouard
ENSMA, France
Eberle Rambo
Technische Universität Braunschweig, Germany
Wolfgang Puffitsch
Technical University of Denmark, Denmark
Leandro Soares Indrusiak
University of York, United Kingdom
Ramon Serna Oliver
TTTech, Austria
Thilo Sauter
Donau-Universität Krems, Austria
Ye-Qiong Song
LORIA, France
Jean-Dominique Decotignie
Swiss Center for Microtechnology, Switzerland
Luis Almeida
University of Porto, Portugal
Jörg Mische
Augsburg University, Germany
Moris Behnam
Mälardalen University, Sweden
Important
dates
Submission deadline: 26th May 2016
Notification of acceptance: 7th June 2016
Submission of camera-ready papers:
17th June 2016
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News And Updates
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11th July 2016: slides from the keynotes are available: MPPA and Argo
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7th June 2016: the list of accepted papers can be found here
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4th April 2016: the submission site is open
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9th February 2016: a keynote on real-time NoCs will be given by Jens Sparsø!
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7th February 2016: accepted papers will be published in the ACM SIGBED Review Special Interest Group on Embedded Systems!
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8th January 2016: a keynote on the Kalray MPPA chip and its use in real-time systems will be given by Benoît Dupont de Dinechin!
Workshop presentation
The Real-Time Networks (RTN) 2016 is a satellite workshop of
the 28th Euromicro
Conference on Real-Time Systems (ECRTS 2016), the premier European
venue for presenting research into the broad area of real-time and
embedded systems.
The RTN workshop is the fourteenth in the series of workshops that
started at the 2002 ECRTS conference. No edition took however place in
2015. To restart a new series of workshops, RTN 2016 focuses on the
current technological challenges around real-time network
infrastructures either between chips or on-chip (NoC). Besides, accepted
papers will be published in SIGBED Review unless authors explicitly refuse
in order to keep material for a later publication in a conference or
journal.
The RTN workshop provides a relaxed forum for both industrial and
academic participants to present and discuss new ideas, new research
directions and to review current trends in the area of real-time
networks and NoC. Schedule will provide significant time for
discussions among the attendees.
The RTN workshop seeking regular research paper or position paper that
should not exceed 6 pages. Areas of interest include, but are not
limited to:
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Real-time network on chips (NoC)
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Real-time message scheduling and mapping over off and on-chip networks (Ethernet, CAN, FlexRay, NoC, etc.)
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Real-time applications (automotive, aerospace, multimedia, etc.): implementation, experimentation and evaluation
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Performance evaluation, simulation and modeling tools of real-time networks (automotive, aerospace, multimedia, etc.)
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Networked embedded systems and sensors, cyber-physical systems, internet of things
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Real-time network management and time synchronization
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Wireless technologies and Sensor Networks (WSNs) and applications
Submission of papers
All papers will be reviewed by the workshop Program Committee and
should be written in English.
All accepted papers will be published in the ACM SIGBED Review Special
Interest Group on Embedded Systems unless authors explicitly refuse in
order to keep material for a later publication in a conference or
journal. By accepting that papers are published in the ACM SIGBED
Review, authors give permission to publish and include the papers in
ACM Digital Library.
Papers should not exceed 6 pages in ACM SIG format,
see http://sigbed.seas.upenn.edu/submit.html.
Research papers should present original research results not published
or submitted for publication in other forums. Authors of accepted
papers agree to attend the workshop and to present their work during
the workshop.
Keynote talks
- Argo - An area-efficient time-division-multiplexed network-on-chip for real-time multicore platforms
Speaker: Professor Jens Sparsø, Department of Applied Mathematics and Computer Science, Technical University of Denmark.
Abstract:
Argo is a network-on-chip (NOC) developed for use in a
multiprocessor platform targeting real-time applications. A
NOC for such a platform must provide guarantees on latency
and bandwidth for the different processor-to-processor
communication flows, and there are several approaches to
achieving this time predictability. Aiming for a small
hardware footprint, we decided on the following baseline for
the design: time-division-multiplexing (TDM) of resources,
static scheduling of traffic and source routing of
packets. The initial research was done in the EU FP7 project
T-CREST (2011-2014), where a first version of a complete
time-predictable multiprocessor platform – named T-CREST
after the project – was developed.
In the field of computer networks, the conventional designer
thinking is one of layering, encapsulation and clean interfaces. In
the NOC-domain this mind-set often results in bulky designs where
those involved seem to have forgotten that the purpose of the NOC is
to move some bits some millimeters on a chip, and that hardware
resources can only be used once (for processing or for communication).
We have taken a more holistic approach, and Argo has a
number of innovations that minimize the area by roughly a factor of 2
compared to other NOCs with similar functionality. Firstly, Argo uses
a novel network interface (NI) architecture where the DMA controllers
that drive the transfer of data across the NOC are integrated with the
TDM scheduling mechanism. This avoids the buffers and the associated
flow-control that is typically found in other NOCs. Secondly, Argo
uses asynchronous routers and exploits their inherent time-elasticity
to tolerate clock skew among the NIs in the different nodes in the
NOC. The talk will provide an overview of the architecture of Argo
and elaborate on the above-mentioned innovations. In addition, the
talk will comment on the efficiency of TDM and static scheduling, an
area where we have learned some interesting lessons.
- Guaranteed Services of the NoC and DDR Memory of the MPPA Processor
Speaker: Benoît Dupont de Dinechin, CTO at Kalray.
Abstract:
The MPPA manycore processor comprises 16 compute clusters with 16 application cores each, and 2 I/O clusters with 4 application cores each. These clusters are connected by a direct network-on-chip (NoC) with source routing and a 2D torus topology. In this presentation, we position the MPPA NoC architectural choices and their alternatives in the areas of switching, routing and flow control, as motivated by implementation simplicity and the ability to guarantee services through the application of network calculus. We explain how the feed-forward premises of network calculus are ensured by the application of classic deadlock prevention techniques. We then present our application of network calculus to the MPPA NoC and its reduction to a linear programming formulation. Finally, we outline how the MPPA NoC guaranteed services can be combined with a suitable DDR memory service policy in order to extend the guaranteed services to the MPPA platform when used in safety-critical applications.
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