{"id":35,"date":"2021-11-05T16:04:16","date_gmt":"2021-11-05T16:04:16","guid":{"rendered":"http:\/\/v2202107152796158410.ultrasrv.de\/?page_id=35"},"modified":"2024-07-10T05:39:33","modified_gmt":"2024-07-10T05:39:33","slug":"conference-program","status":"publish","type":"page","link":"https:\/\/www.ecrts.org\/conference-program\/","title":{"rendered":"Program"},"content":{"rendered":"\n
Time<\/th>Tue, July 9<\/th>Wed, July 10<\/th>Thu, July 11<\/th>Fri, July 12<\/th><\/tr><\/thead>
08:00-08:45<\/td>Registration<\/td>Registration<\/td>Registration<\/td><\/td><\/tr>
08:45-09:00<\/td><\/td>Opening<\/td><\/td><\/td><\/tr>
09:00-10:00<\/td>Workshop Day<\/td>Keynote – Adrien Gauffriau, Airbus<\/a><\/strong><\/td>Keynote – Francisco J. Cazorla, BSC<\/a><\/strong><\/td><\/td><\/tr>
10:00-10:30<\/td><\/td>Coffee Break<\/td>Coffee Break<\/td>Coffee Break<\/td><\/tr>
10:30-12:00<\/td>Workshop Day<\/td>Session 1: OS and Hypervisor Technology<\/a><\/td>Session 3: Real-Time on GPUs<\/a><\/td>Collaborative Session<\/a><\/td><\/tr>
12:00-13:30<\/td><\/td>Lunch Break<\/td>Lunch Break<\/td>Lunch Break<\/td><\/tr>
13:30-15:00<\/td>Workshop Day<\/td>Session 2: Resource Sharing and Task Dependencies<\/a><\/td>Session 4: Managing Resource-Constrained Devices<\/a><\/td>Session 5: Response Time Analysis<\/a><\/td><\/tr>
15:00-15:30<\/td><\/td>Coffee Break<\/td>Coffee Break<\/td>Coffee Break<\/td><\/tr>
15:30-17:00<\/td>Workshop Day<\/td>Real-Time Pitches<\/a><\/td>Industrial Challenge<\/a><\/td>Session 6: Network Analysis<\/a> + Concluding Remarks<\/strong><\/td><\/tr>
Social Events<\/td>First-Timer Reception<\/a><\/td>Poster & Demo Session and Reception <\/strong>
(17:00-19:00)<\/td>		Social Activity and Conference Dinner<\/a><\/strong><\/td><\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n
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Keynote – Adrien Gauffriau, Airbus. AI in Critical Avionics: Certification and Embedded Challenges<\/h2>\n\n\n\n

Chair: Julien Forget, Universit\u00e9 de Lille<\/p>\n\n\n\n

Abstract:<\/strong> Given the future challenges for Airbus in smart automation and decarbonization, this presentation will explain how artificial intelligence will play a crucial role in our upcoming products. The keynote will then focus on the paradigm shift brought about by the design of AI-based systems, and the implications in terms of algorithms, hardware architecture, and required computational power. Especially we will propose to focus on actual standardization frameworks proposed by EASA and WG114. In the third part, we will address the need to ensure semantic preservation properties (one of the major pillars required for the certification), illustrated by our work on extending the ONNX format. <\/p>\n\n\n\n

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Bio: <\/strong>Adrien Gauffriau is an expert in embedded artificial intelligence, currently working at Airbus. He is an alumnus of Ecole Centrale de Nantes and holds a Master\u2019s degree in Critical Embedded Systems from Supa\u00e9ro.<\/p>\n\n\n\n

Adrien has a distinguished career in avionics, having developed the Flight By Wire software for the Airbus A350. He has also conducted pioneering work on the use of multi-core and many-core processors for critical systems. Presently, he supports various Airbus projects aiming to deploy onboard artificial intelligence and computer vision technologies to enhance aircraft safety and expand operational capabilities. Additionally, Adrien is actively involved in establishing new industrial standards (ARP6983, EUROCAE WG114 \/ SAE G34)  for the development of machine learning systems within critical avionics systems.<\/p>\n<\/div>

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Keynote – Francisco Cazorla, BSC. Software Timing Verification & Validation on Modern Multi-Processor System on Chip processors (MPSoCs)<\/h2>\n\n\n\n

Chair: Renato Mancuso, Boston University<\/p>\n\n\n\n

Abstract:<\/strong> We are witnessing increasing autonomy requirements in critical embedded systems (CES) a in a wide range of domains, including automotive, space, avionics, and robotics. Autonomy heavily builds on complex AI software stacks that have high computing performance requirements. MPSoCs are capable of providing the required performance levels. However, the complexity of MPSoC hardware and AI-based software poses significant challenges on functional safety and, in particular, software timing verification and validation (V&V). The source of the problem lies in the non-obvious interactions among applications in the access to MPSoC\u2019s shared resources that can cause arbitrarily large impact on performance.<\/p>\n\n\n\n

In this talk I will delve into two sets of approaches aimed to mitigate the risks associated to the increasing complexity of MPSoCs on software timing behavior. First, in terms of software-only approaches I will cover analyses, methods, and technologies that addresses some key timing V&V challenges including the generation of stressful scenarios relevant for Worst-Case Execution Time (WCET) estimation, enabling WCET estimation in the context of multi-provider software with IP restrictions, and monitoring contention among tasks.  And second, in terms of hardware solutions, I will cover strategies to extend high-performance MPSoCs with features to enable their use in safety-relevant scenarios without impacting performance including several modules for increased observability and quota control, and modules for flexible performance testing.<\/p>\n\n\n\n

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Bio: <\/strong>Francisco J. Cazorla is co-head of the CAOS (Computer Architecture – Operating System) research group at the Barcelona Supercomputing Center (BSC) that currently counts more than 50 members. Dr. Cazorla\u2019s research interests cover hardware and software designs and associated analyses for multicore-based high-performance and high-integrity systems. On these topics Dr. Cazorla has coordinated several EU-funded research projects (PROARTIS, PROXIMA, MASTECS), projects funded by the European Space Agency, and bilateral projects between BSC and industry (e.g. Airbus, Thales, Rockwell Collins, IBM, Intel, \u2026). Dr. Cazorla has been ERC Consolidator grant holder and in early 2020 he co-founded Maspatechnologies S.L., a spin-off from BSC focused on timing analysis for real-time multi-core systems. Maspatechnologies S.L. was sold to DANLAW Inc in November 2022. <\/p>\n<\/div>

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Session 1: OS and Hypervisor Technology<\/h2>\n\n\n\n

Chair: Giorgio Buttazzo, Scuola Superiore Sant\u2019Anna<\/p>\n\n\n\n