15th International Workshop on Worst-Case Execution Time Analysis (WCET 2015). Lund, Sweden. 7th July.


Program Chair

Francisco J. Cazorla Leader of the CAOS group at BSC and researcher at IIIA-CSIC

Program Committee

Benoît Triquet, Airbus
Björn Lisper, Univ. College of Mälardalen
Christine Rochange, IRIT
Claire Maiza, Grenoble INP/Verimag
Damien Hardy, IRISA
Enrico Mezzetti, Univ. of Padua
Franck Wartel, Airbus
Guillem Bernat, Rapita Systems
Heiko Falk, TU Hamburg-Harburg
Isabelle Puaut, IRISA
Jaume Abella, BSC
Luca Fossati, ESA
Luis Miguel Pinho, CISTER
Martin Schoeberl, DTU
Peter Puschner, TU Wien
Tullio Vardanega, Univ. of Padua

Steering Committee

Guillem Bernat, Rapita Systems Ltd., UK
Björn Lisper, Univ. College of Mälardalen
Isabelle Puaut, IRISA
Peter Puschner, TU Wien


Important Dates

  • Submission Deadline: May 1st, 2015
  • Notification: 22nd May, 2015
  • Final Version Deadline: 9th June, 2015
  • Workshop: 7th July, 2015


July 2015 Lund, Sweden

The 15th International Workshop on Worst-Case Execution time Analysis (WCET 2015) is a satellite workshop of the 27th Euromicro Conference on Real-Time Systems (ECRTS 2015) , the premier European venue for presenting research into the broad area of real-time and embedded systems.



WCET workshop is the reference forum for academics, practitioners and industrials in any aspect related to the timing analysis of computer systems. While in the past timing analysis has been a topic mainly for real-time systems, recently it has becoming crucial in other domains dealing with timing guarantees. This includes among other mobile
computing and high-performance computing. This edition of the WCET workshop, besides papers targeting traditional WCET analysis, encourages submissions focused on less rigorous and mature timing analysis techniques on complex multicore and manycore heterogeneous, usually COTS, architectures. For such complex architectures Execution Time Bound (ETB) estimates are derived rather than WCET estimates in the strict sense.  ETB estimates are intrinsically less reliable than WCET estimates.



This workshop seeks original contributions on topics that include but are not limited to:

  • WCET/ETB analysis for multi- and many-core systems
  • WCET/ETB analysis for multi-threaded applications
  • WCET/ETB analysis for COTS processors
  • Case studies, and industrial experience of WCET/ETB analysis
  • Timing Analysis and safety standards
  • Different approaches to WCET/ETB computation
  • Probabilistic timing analysis
  • Tools for WCET/ETB analysis
  • Timing-predictable operating systems and processor designs
  • Compiler-based optimization of worst-case timing
  • Low-level timing analysis, modeling and analysis of processor features
  • Flow analysis for WCET, loop bounds, infeasible paths
  • Integration of timing analysis and schedulability analysis
  • Integration of timing  analysis in development processes
  • Methods and benchmarks for timing analysis evaluation

Innovative, controversial statements or that present new approaches are specially sought.